1. Field of the Invention
This invention generally relates to a multi-chip module semiconductor device, and, in particular, to an arrangement of bonding pads on the chips of such a MCM semiconductor device.
2. Description of the Prior Art
A multi-chip module (MCM) semiconductor device is well known in the art and it includes a plurality of bare semiconductor integrated circuit chips, which are not individually packaged, but packaged in a common package. Such MCM semiconductor devices may be generally categorized into two types, i.e., (1) ceramic package type and (2) plastic package type.
The ceramic package type is used where heat production and high reliability are primary concerns, such as a CPU board for use in a work station, wherein all of LSI's are contained in the same package so as to obtain an increased speed by reducing the propagation delay of a signal, and MCM semiconductor devices for use in automobiles. On the other hand, the plastic package type is used where heat production and high reliability are not primary concerns so as to attain an increased yield, a reduction in the overall cost, an upgraded function due to integration of a plurality of functions, etc.
Now, merits of such MCM devices will be described with reference to a table illustrated in FIG. 6, which illustrates merits of MCM devices in comparison with a conventional single chip semiconductor device.
First, regarding yield, the conventional single chip approach is disadvantageous because the chip size tends to become larger should the same function as that of a MCM device be provided by a single chip device. Described more in detail, as shown in FIG. 6, in the case of the conventional single chip approach, even if a single defect is present in the chip as indicated by "X", the chip as a whole becomes defective. On the other hand, in the case of the MCM approach, even if one or more defects are present, as long as a chip A, which corresponds to the left-hand half section of the conventional single chip, is a good chip (as indicated by circles in FIG. 6), it can be combined with another good chip B, which corresponds to the right-hand half section of the conventional single chip, thereby providing an operative complete device. Thus, the MCM approach allows to obtain an increased yield.
FIG. 3 is a graph illustrating a relationship between the chip size and the yield. It can be seen from FIG. 3 that the smaller the chip area, the higher the yield and the lower the chip cost. On the other hand, since an increase in the assembly cost as the chip area becomes smaller is rather small, the total cost continues to decrease until it levels off by advancing the degree of multi-chip approach. Accordingly, as specifically illustrated in FIG. 3, in the case of manufacturing 16M DRAMs, it can be understood that the total cost can be significantly reduced by combining smaller capacity DRAM chips, such as 8M and 5.3M DRAMs, into a 16M DRAM rather than manufacturing a 16M DRAM as a single chip. Besides, in the case of a MPU, the total cost can be significantly reduced similarly by adopting the multi-chip approach rather than providing all of CPU, FPU, cache memory and the like on a single chip.
Regarding a functional aspect, in the conventional device, since only a single IC can be contained in a single package, only a single function can be provided per package. On the other hand, in the case of the MCM approach, since a plurality of ICs can be provided in the same package, a variety of semiconductor devices having a multiplicity of functions and/or an upgraded function can be provided. For example, there can be provided a 8M bit/package DRAM by using two 4M DRAMs, and a semiconductor device including a CPU and a FPU contained in the same package can be manufactured without changing the process rules.
However, in accordance with the conventional MCM approach, in particular in the case of plastic sealed MCM approach, when sealing a chip mounted on a tab with a resin, the arrangement of tabs and leads needs some considerations as shown in FIG. 4. In the specific arrangement of tabs and leads shown in FIG. 4, difficulty may be encountered in determining a layout because of increased constraints in providing leads in an area sandwiched between the two adjacent tabs. Because of such constraints, the resulting package tends to become larger. In the specific structure shown in FIG. 4, a chip 57 is directly mounted on a tab 52 and a plurality of leads 55 are wire-bonded to the chip 57 by bonding wire 61. All of the chips 57 are commonly sealed in a resin package 56.
FIGS. 5a and 5b illustrate a prior art approach trying to reduce the constraints in the arrangement of leads as described above. However, this prior art approach increases complication in the shape of lead pattern, which, in turn, causes the wire bonding to be difficult to implement. In the structure shown in FIGS. 5a and 5b, a chip 117 is directly mounted on a corresponding tab 112 and a tab connector 113 connects the two tabs 112 together. Leads 115 are arranged around each of the tabs 112 and connected to corresponding chips 117 by bonding wire 121. All of these elements are sealed in a common resin package 116.